January 2016:

Certus announces 2 new classes of High Voltage, low capcaitance and low leakage, ESD protection structures, in TSMC 180nm Gen2 process.

TSMC 180nm BCD Low Cap High Voltage ESD Protection

July 2015

Certus Announces release of 5V Open-Drain IO's (ODIO) in TSMC 28nm Processes using only 1.8V Transistors.  2kV IEC compliant ODIO available for use in external connectors (i.e USB, HDMI, etc). An addendum to the existing 28nm TSMC 28nm GPIO and HDMI/LVDS/Analog Library.

TSMC 28nm Custom IO and ESD Library: Multi-Voltage 


October 2013:

Catch us at the 4th Annual Silicon Valley IP Users Conference

View the Certus Presentation at the conference here:

Conquering your fears of Custom IP


January 2015:

Certus announces the silicon validated worlds smallest area IO for ESD protection of analog, HDMI and high speed digital circuits in 40nm TSMC. The ESD and power bussess are completely underneath the Bondpad, making the IO cell only 60um x 50um wide/pitch.

TSMC 40nm: HDMI, LVDS, RF and Analog Pads, worlds smallest footprint cell

Oct 2014:

Catch us at the 2014 Silicon Valley IP Users Conference

If you missed it, make sure to catch the video of  Stephen Fairbanks, Managing Director at Certus Semiconductor, present: How Custom IO can Benefit You

August 2014:

Certus announces a silicon validated series of Extreme High Voltage design solutions for building 10-30V applications in a variety of standard foundry low voltage CMOS processes.

TSMC Processes: Exotic High Voltage ESD Protection

June 2014:

Catch us at DAC 2014 (Design Automation Conference)

and more importantly, do not miss our Stars of IP Party

January 2014:

Certus release a silicon Validated 28nm Pad and IO Library in 28nm TSMC.  This unique Library includes dynamic mulit-voltage VDDIO from 1.8V to 3.3V, robust ESD and even 2kV IEC, and an extremely flexible feature set.

TSMC 28nm Custom IO and ESD Library: Multi-Voltage 

October 2013:

Catch us at the Smeico IMPACT Conference 2013

View the Certus Presentation at the conference here:

Do you know what ESD really is?

June 2013:

Catch us at the "Stars of IP Alliance" at DAC 2013

April 2013:

Stephen Fairbanks, Managing Director at Certus-Semiconductor is interviewed by Warren Savage of Take Five, a series of interviews with leaders in the semiconductor industry.

Warren Savage and Stephen Fairbanks, "Take Five with Warren"

Also Stephen presented at the GSA (Global Semiconductor Alliance) 3D-IC working group.

3D IC Integration and ESD

March 2013:

Stephen Fairbanks, Managing Dirertor at Certus Semiconductor, will offer a webinar for the Constellations Educational Webinar Series.

EOS vs. ESD: Understanding the Confusion

January 2013:

Certus release a silicon Validated 65nm Pad and IO Library in 65nm Global Foundries.  Includes LVDS RX/TX PHY macros.

GF 65nm GPIO and LVDS Library (with RF and Analog)

September 2012:

Catch us at the IP Extreme Constellations Conference Oct 4

http://www.ip-extreme.com/news/constellations2012.shtml 

Watch Stephen Fairbanks, Managing Director at Certus Semiconductor offer a presentation at the conference:

The Black Magic of ESD and I/O Design

April 2012:

Certus Semiconductor is proud to announce its membership with IPextreme's Constellations  Program.

IPextreme Announces new IP database for Constellations Program

September 2011:

Certus Semiconductor makes available TSMC 28nm ESD Libraries based on Freescale IP.

Feb 2011:

Certus Semiconductor makes available >2kV HBM/500V CDM  ESD protection library in TSMC 40nm Technology for 28Gbit CMOS interfaces.

August 2009:

 Certus Semiconductor announces a Technologies transfer and License agreement with Freescale Semiconductor.  Freescale grants Certus the right to utilize and market ESD and IO products and services utilizing Freescale’s industry leading ESD technology and IP.

Certus Freescale Press Release, August 2009