The qualification requirements for integrated circuits for both JEDEC [1] and the Automotive Electronics Council (AEC) [2], require ESD testing … Read More

Certus is excited to announce that its 1.2V/3.3V wire-bond I/O library in TowerJazz’s 65nm process is silicon-verified, and exceeding expectations! … Read More

DAC is right around the corner and this could possibly be the last one in San Francisco for a while … Read More

Introduction In previous blog posts, we have discussed the Human Body Model (HBM) waveform and traditional HBM pin combinations. In … Read More

Traditionally there have been three test methods for evaluating the robustness of integrated circuits to electrostatic discharge (ESD) damage during … Read More

Certus Semiconductor is a unique company. Their customer centric business model ensures customer success at many levels. Certus is staffed … Read More

In an earlier blog the basic HBM waveform was discussed and Figure 1 was used to introduce how the waveform … Read More

Introduction In a previous blog, HBM Basic Waveform, we discussed the circuit diagram and basic waveform for the Human Body … Read More