CDM Dependence on Device Capacitance
Introduction In a previous blog “Field Induced CDM Explained” I discussed what happens during the CDM test. This included the … Read More
Low-Leakage Digital Design on SkyWater 90nm
A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library As semiconductor designs continue to diversify, many … Read More
Modern Trends in I/O and ESD Design
It was very clear at the recent 2025 TSMC OIP Ecosystem Forum that the semiconductor I/O landscape has undergone a profound transformation … Read More
Field Induced CDM Explained
Preface This blog post is an update of an article originally published in 2008 in the now defunct Conformity magazine. … Read More
One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
May 28, 2025 Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer … Read More
Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
April 23, 2025 Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions [Santa Clara, CA … Read More
Unlocking High-Speed Connectivity with Certus Semiconductor’s LVDS Transceiver on GlobalFoundries 12LP/LP+
In today’s data-driven world, high-speed, low-power communication is essential. Certus Semiconductor’s LVDS Transceiver delivers exactly that—optimized for GlobalFoundries’ 12nm CMOS … Read More
Join the Discussion: Foundry ESD Checks & Standardized ESD Compact Models at US-IEW 2025
The ever-evolving landscape of semiconductor design demands robust ESD protection strategies that balance performance, reliability, and compliance. At the 2025 … Read More
Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
Certus Semiconductor is pleased to announce that it has begun 2025 with the delivery of a radiation-hardened by design I/O … Read More