In an earlier blog the basic HBM waveform was discussed and Figure 1 was used to introduce how the waveform was formed. The JS-001 HBM standard shows a somewhat more detailed figure, which is reproduced in Figure 2. The two figures are essentially identical except for the Charge Removal Circuit in Figure 2. In this blog the function of the Charge Removal Circuit will be discussed, including its evolution as more has been learned about the details of how HBM test system work.
The charge removal circuit has been in various HBM standards for many years. The JEDEC HBM standard, JESD22-A114, and the military HBM standard, MIL-STD-883 Test Method 3015 included a simple switch in parallel with the device under test (DUT). The ESDA HBM standard, ANSI/ESD STM5.1, included the switch but required the switch be in series with at least a 10 kΩ resistor. The purpose of this circuit was to remove any remaining charge on the device being tested and on the test fixture before the next pulse. The switch was to be closed after the HBM pulse and then opened again before the next pulse. The resistor required in the ESDA standard was to limit current while removing residual charge. It is likely that equipment suppliers always included a current limiting resistor in the charge removal circuit as part of good system design.
The need for some form of charge removal circuit employed during the HBM pulse began to emerge with the presentation of two papers during the same session at the 2004 EOS/ESD Symposium. One involved a low level, but long-lived, current which occurred after the HBM pulse and the second involved voltages which appeared across the DUT before the HBM pulse.
In the first paper  it was found that after the main HBM current pulse there was a “Trailing Pulse” which lasted up to 700 us. The current is shown conceptually in Figure 3. To understand the features in Figure 3 it is necessary to know that a real relay has properties that differ from an ideal, fully off versus fully on switch. HBM testers frequently use high pressure gas mercury whetted relays. When such a relay is activated at high voltage the initial conductivity is not when the relay contacts actually touch, but when an arc forms between the relay contacts. The main HBM pulse is totally carried by this arc. Only 10s of us later do the relay’s contacts make physical contact, resulting in a second, but smaller HBM pulse. This secondary pulse has long been known and JS-001 requires that its peak current be less than 15% of the main HBM pulse. What the paper by Meuse et.al found was a long trailing current pulse of almost constant magnitude which lasted for 700 us and could be 100s of uA in magnitude.
The source of this current is the result of another artifact of a gas filled relay. After the arc which carried the initial HBM current pulse the gas in the relay remains ionized for 100s of us. The ionized gas provides a current path to the device under test all the way back to the high voltage power supply.
The trailing current could charge up the input on the DUT all the way up to the breakdown voltage of the protection diodes. The result was a sustained voltage on the input gate oxides, which resulted in a shift in transistor threshold which put input high and input low values out of specification. The result was a false HBM failure. The failure was a false failure because it was not caused by the HBM pulse itself but by the trailing pulse current which would not be present in a real world HBM event.
There are two ways to fix the issue with trailing pulses, and these are both shown in Figure 4. The more elegant is to place an extra relay, S2, between the >1 MΩ resistor and the 100 pF capacitor. Relay S2 would be closed during the charging of the 100 pF capacitor. S2 would then be opened before relay S1 is switched to initiate the HBM pulse. Since S2 is opened when the potential on each side of the relay is the same there is no arc and therefore no ionization in the relay. The DUT is therefore effectively isolated from the high voltage supply and there will be no trailing current. This is, however, a major hardware change and is not always practical.
An easier method is to place a 10 kΩ or greater resistor in parallel with the DUT during, not just after, the HBM pulse. If the charge removal circuit in Figure 2 is a resistor adding the resistance during the HBM pulse is simply a software change. The 10 kΩ resistor will drain charge off of the DUT during any trailing pulse, preventing voltage from building up across the DUT.
The second paper  which led to the adoption of the 10 kΩ resistor for charge removal during HBM testing concerned voltages across the DUT before the HBM pulse. Dynamic power supply clamps were found to be failing if the power rail being tested had low capacitance and low leakage. An example of a dynamic power supply clamp is shown in Figure 5. During normal operation the inverter chain and RC network keep the large nMOS (BigFET) device off. During handling and HBM testing power is not applied so the VDD to VSS voltage is assumed to be zero. A positive ESD event on VDD will rapidly increase the potential on VDD with respect to VSS. The RC network will tend to hold the input to the first stage of the inverter chain low for an RC time constant. The inverter chain will therefore hold the gate of the large nMOS device high. With the gate high the large nMOS device will provide a non-damaging current path for the HBM stress.
Experiments with vacuum relays , which do not leak due to gas conductivity, showed that the pre HBM pulse voltage was due to the varying capacitance as the relay closed, but before the arc formed to create the HBM event. The mechanism can be understood with the aid of Figure 7. The figure consists of the 100 pF capacitor in the HBM model, the capacitance across the relay, represented by a variable capacitor and the DUT, represented by a Zener diode which has its own parasitic capacitance in addition to tester capacitance. Before the HBM test system starts an HBM test event the 100 pF capacitor is charged to the HBM test voltage, for example, 1000 V. With 1000 V across the 100 pF capacitor the voltages across the relay capacitance and the DUT capacitance must be 1000 V. It is assumed that the relay capacitance is much lower than the DUT capacitance so that most of the voltage is dropped across the relay. Additionally, any leakage, RDUT, in the DUT will tend to maintain low voltage across the DUT during the relatively long charging time of the 100 pF capacitor. The situation changes when the relay begins to close to initiate an HBM test pulse. As the relay closes and the relay contacts get closer together the relay capacitance increases with a time scale of 10s to 100s of us. As the relay capacitance increases more charge is needed in the relay to maintain the voltage across the relay since V =qC. On the 100 pF side of the relay the charge must come from the 100 pF, slightly reducing the voltage across the 100 pF capacitor. On the DUT side the charge must come from the DUT. If the DUT resistance is very high (low leakage) the DUT capacitance will become charged and the voltage across the DUT will rise, as was shown in . The lower the DUT capacitance and the lower the DUT leakage the larger the voltage rise will be.
The next question on the pre-pulse voltage is; should this effect be removed from the tester because it doesn’t represent real life or is there a pre-pulse voltage during a real HBM event and ESD protection structures must be designed to protect even when a pre-pulse voltage is present. A 2006 EOS/ESD Symposium paper addressed this issue . This investigation suggested that the pre-pulse voltage was an effect that can occur in a real life ESD event, but its magnitude will likely be much smaller in a real-world event. The approach speed of the contacts in a relay will likely be orders of magnitude faster than a person is likely to be able to duplicate while handling integrated circuits. The conclusion was that it was reasonable to remove or reduce the pre-pulse voltage in an HBM test system.
The most effective way to ensure that voltage does not build up across the device is to add a resistance which is low enough to maintain zero voltage across the DUT but high enough not to adversely affect the HBM pulse properties. A 10 kΩ resistor has been deemed to be a reasonable choice.
To demonstrate how much the presence of a 10 kΩ shunt resistor changes the HBM stress current SPICE simulations were made of the current through hypothetical DUT. The DUT was represented by a diode with a 100 V reverse breakdown and a 100 Ω resistance above reverse breakdown. The results are shown in Figure 8. This is a particularly bad ESD protection scheme, but shows how little the addition of the 10 kΩ shunt degrades stress on the device under test.
In summary, a 10 kΩ resistor across the device under test during HBM testing can remove unwanted stress after the HBM pulse from trailing pulse current but will remove pre-pulse voltage which can prevent some types of dynamic clamps from functioning properly. This is accomplished with minimal effect on the HBM stress current.
Source: SRF Technologies - Post