High Voltage (>10V) RF and Analog Interfaces for Standard Low Voltage CMOS TSMC Processes

 

Authors: Pradeep Thiagarajan and Stephen Fairbanks

We live in a digital age, but the world around us is very much analog. Sensors and signal converters exist at the boundaries of digital and analog components, and these boundaries create voltage barriers many times. The need for high performance computing has further forced the foundry technology advancement into lower voltage and power processes. However, sensors have not scaled as fast. Many modern MEMs and RF applications still need voltage levels much greater than 10V for normal operation. Historically, making such diverse technology requires additional discrete components into a system board to down-shift the higher voltage RF and Analog domains to the low voltage CMOS products.

Over the past 12 years, Certus Semiconductor has helped its customers build unique high voltage RF, analog and MEMs interfaces directly to TSMC low voltage processes, by leveraging unique qualities in TSMC processes, particularly in CMOS 22nm to 65nm nodes. Two notable examples included a 20V and 24V Analog IP in 65nm LP and 55nm ULP, and a >100V differential RF switch using -18V to 30V single-ended RF PAD, developed in 40nm LP. These interfaces included full ESD protection including >2kV HBM and >500V CDM. These high voltage solutions were designed in the standard TSMC CMOS process nodes, with no extra masks, technology or layers. This capability has enabled PMIC, MEMs and RFIC developers to bring directly to die, any high voltage signal that would have otherwise required several off-chip components to downgrade the voltage levels to <5V, thus providing customers a direct competitive edge in the marketplace. Certus customers have successfully taped out several variations of these solutions in various TSMC nodes, and now have a system in place for tailoring and optimizing layers, targeting voltage levels and ESD levels for their applications, with 100% 1st silicon success. In some cases, it has further provided them with a system level ESD solution at board level for these high voltage signals.

Certus Semiconductor utilizes Siemens’ Calibre DRC deck as a design guide tool to track exactly how the specialized layout is completed. Analog FastSPICE Platform (AFS) is used to create and verify the parasitic models for final delivery to customers. AFS is certified across TSMC process technologies from mature to advanced CMOS TSMC technologies.

In this presentation, Certus will detail some of these specialty High Voltage ESD and RF solutions developed that are unique to TSMC processes, as well as how they can also be tailored for additional applications.

 

Source: TSMC 2023 OIP Ecosystem Forum