General Purpose I/O

  • Certus offers 1.8V, 3.3V and switchable 1.8V/3.3V General-Purpose IO (GPIO) solutions.
  • Features include:
    • Dedicated 1.8V & 3.3V cells or dynamically switchable 1.8V/3.3V cell
    • Multiple drive strengths (dedicated cells or selectable)
    • Supply sequency independence
    • Output enable/disable (HiZ when disabled)
    • Schmitt trigger input
    • Selectable pull-up or pull-down resistor
    • Flexible metal stack and cell pitch variations
    • Wirebond & Flip-Chip support
    • ESD Protection of 2KV HBM, 500V CDM1
    • 1CDM rating is a function of package size. Rating shown is for nominal packages.

snap to page section GPIO

GPIO

Pin

Description

VDDIO 1.8V, 3.3V or switchable 1.8V/3.3V
VREF 1.8 Reference Supply (for 3.3V operation)
VDD Core Supply
VSS 0V GND
DIN Core data to PAD
OE Output Enable (HiZ when disabled)
DS Drive strength select (where available)
DOUT PAD data to core
PE Pull up/down resistor enable
PUD Pull-up/pull-down resistor select
PAD Bond pad to outside world

snap to section GPIO spec

Key GPIO Specifications (Wide Range JESD 8-5A based)

Description

Min

Nom

Max

Units

VDDIO IO supply voltage (3.3V mode) 3.0 3.3 3.6 V
IO supply voltage (1.8V mode) 1.62 1.8 1.98 V
Tj Junction temperature range -40 25 125 °C
VIH Input logic high 0.7*VDDIO - - V
VIL Input logic low - - 0.2*VDDIO V
VOH Output logic high (IOH = -100mA) VDDIO-0.2 - - V
VOL Output logic low (IOL = 100mA) - 0.2 V
Vt+ (Hys) Hysteresis positive going threshold 0.25*VDDIO 0.75*VDDIO V
Vt- (Hys) Hysteresis negative going threshold 0.15*VDDIO 0.65*VDDIO V
ΔVt (Hys) Hysteresis voltage 0.1*VDDIO 0.6*VDDIO V
HBM HBM ESD rating 2 3 KV
CDM CDM ESD rating 500 600 V

snap to section GPIO TSMC offer

GPIO TSMC Technology Offerings

Feature

180nm

130nm

65nm

28nm

22nm

16/12nm

VDDIO 1.2-1.8V 3.3V 1-3.3V 1.8/3.3V selectable 1.8/3.3V selectable 1.8/3.3V selectable
VDD 1.2-1.8V 1.5V 1.2V 0.9V 0.9V 0.8V
Drive Strengths 2 1 1 3 3 4
Max Frequency 50MHz 50MHz 100MHz 150MHz 150MHz 235MHz
Schmitt Yes Selectable Yes Yes Yes Yes
PU/PD resistor 60KΩ 60KΩ 50KΩ 60KΩ 60KΩ 50KΩ
Substrate Isolation Yes No Yes No No No
Fail Safe No No Yes Yes No No
Package Flip-Chip Wirebond Wirebond Wirebond Wirebond Flip-Chip
Cell pitch 60um 140 um 55um 55/25/20um 55um 25um

snap to section opendrain io

I2C I/O

  • Our libraries include an I2C Open Drain IO, up to 3.3V-5V tolerant, supporting Fast Mode (400Kbps) and Fast Mode+ (1Mbps) data rates. Fully compatible with the Certus GPIO library, this cell can be configured across a broad range of open-drain interfaces, resistive and capacitive loads. Our Open Drain cell is I2C, SMBUS, DDC, CEC and HPD compliant.
  • Features include:
    • Output enable
    • Hysteresis input
    • Fail Safe
    • Power-on sequence independence
    • External resistor support of 1KΩ-50KΩ
    • ESD protection of 2KV HBM, 500V CDM1
      1CDM rating is a function of package size. Rating shown is for nominal packages.

snap to section opendrain i2csmbus ddcio

I2C Open Drain I/O

Pin

Description

VDDIO 1.8V - 5V supply
VDD Core supply
VSS 0V GND
OE Output Enable (HiZ when disabled)
C Reflects signal level from PAD
PAD Bond pad to outside world

snap to section key i2c spec

Key I2C Specifications

Description

Min

Nom

Max

Units

VDDIO IO supply voltage (3.3V mode) 3.0 3.3 3.6 V
IO supply voltage (1.8V mode) 1.62 1.8 1.98 V
Tj Operating temperature range (junction) -40 25 125 °C
VIH Input logic high (3.3V mode) 2.1 - - V
Input logic high (1.8V mode) 1.1 - - V
VIL Input logic low (3.3V mode) - - 0.7 V
Input logic low (1.8V mode) - - 0.4 V
VOH Output logic high @-3mA (3.3V mode) - - 3.6 V
Output logic high @-2mA (1.8V mode) - - 1.98 V
VOL Output logic low @3mA (3.3V mode) 0 - 0.4 V
Output logic low @2mA (1.8V mode) 0 - 0.4 V
F Clock frequency (3.3 & 1.8V Fast Mode) - 400 KHz
Clock frequency (3.3 & 1.8V Fast Mode+) - 1 MHz

 

snap to section opendrain tsmc offer

I2C Open Drain I/O TSMC Technology Offerings

Feature

180nm

130nm

65nm

28nm

22nm

16/12nm

VDDIO - 3.3V 3.3V, 5V tol 3.3V, 5V tol 3.3V 3.3V, 5V tol
VDD - 1.5V 1.2V 0.9V 0.9V 0.8V
Max Frequency - 1MHz 1MHz 1MHz 1MHz 1MHz
Schmitt - Yes Yes Yes Yes Yes
Fail Safe - Yes Yes Yes Yes Yes
Package - Wirebond Wirebond Wirebond Wirebond Flip-Chip
Cell pitch - 140 um 55um 55/25/20um 55um 25um

snap to section rgmii io

RGMII I/O

  • Advanced Certus IO libraries include a 1.8V/2.5V Reduced Gigabit Media Independent Interface (RGMII) compliant IO cell.
  • Cell features include:
    • Dynamically switchable 1.8V & 2.5V VDDIO support
    • Output enable (HiZ when disabled)
    • Hysteresis receiver
    • Full interoperability with GPIO library
    • ESD protection of 2KV HBM, 500V CDM1
      1CDM rating is a function of package size. Rating shown is for nominal packages.

snap to section key rgmii spec

Pin

Description

VDDIO 1.8V/2.5V switchable
VDD Core Supply
VSS 0V GND
DIN Core data to PAD
OE Output Enable (HiZ when disabled)
DOUT PAD data to core
PAD Bond pad to outside world

Key RGMII Specifications

Description

Min

Nom

Max

Units

VDDIO IO supply voltage (2.5V mode) 2.25 2.5 2.75 V
IO supply voltage (1.8V mode) 1.62 1.8 1.98 V
Tj Operating temperature range (junction) -40 25 125 °C
VIH Input logic high (2.5V mode) 1.6 - - V
Input logic high (1.8V mode) 1.1 - - V
VIL Input logic low (2.5V mode) - - 0.6 V
Input logic low (1.8V mode) - - 0.4 V
VOH Output logic high @-1mA (2.5V mode) 2.0 - - V
Output logic high @-0.5mA (1.8V mode) 1.35 - - V
VOL Output logic low @1mA (2.5V mode) 0 - 0.4 V
Output logic low @0.5mA (1.8V mode) 0 - 0.4 V
F Clock frequency (2.5V & 1.8V modes) - 125 MHz

 

snap to section rgmii tsmc offer

RGMII TSMC Technology Offerings

Feature

180nm

130nm

65nm

28nm

22nm

16/12nm

VDDIO - - - 1.8V, 2.5V 1.8V, 2.5V 1.8V, 2.5V
VDD - - - 0.9V 0.9V 0.8V
Frequency - - - 125MHz 125MHz 125MHz
Schmitt - - - Yes Yes Yes
Package - - - Wirebond Wirebond Flip-Chip
Cell pitch - - - 55/25/20um 55um 25um

snap to section lvds tx rx

LVDS TX & RX

  • Select libraries feature LVDS TX and RX cells
  • Features include:
    • Output / Input enable
    • Built-in 100Ω RX termination resistor
    • Fault-safe mode for shorted or open RX pins
    • Internally generated common mode reference (no external pin required)
    • Power-on sequence independence
    • ESD protection of 2KV HBM, 500V CDM1
      1CDM rating is a function of package size. Rating shown is for nominal packages.

Pin

Description

VDDIO 2.5V-3.3V
VDD 1.2-1.5V
VSS 0V GND
OE Output Enable (HiZ when disabled)
IE Input Enable (last known state when disabled)
DTX TX data to transmission line
DRX RX data to core
TXP Positive TX signal
TXN Negative TX signal
RXP Positive RX signal
RXN Negative RX signal

 

snap to section key lvds spec

Key LVDS Specifications (3.3V library)

Description

Min

Nom

Max

Units

VDDIO IO supply voltage 3.0 3.3 3.6 V
VDD Core supply voltage 1.35 1.5 1.65 V
Tj Operating temperature range (junction) -40 25 125 °C
VOCM Output common mode voltage 1.22 1.25 1.26 V
VICM Input common mode voltage 0.2 1.2 2.8 V
VOD Output differential voltage 270 250 410 mV
VID Input differential voltage 75 100 mV
TpHL Output propagation delay Hi to Low (RL = 100Ω) 1.1 1.5 2.25 ns
TpLH Output propagation delay Low to Hi (RL = 100Ω) 1.1 1.5 2.25 ns
FOM

Maximum Output frequency

200 MHz
FIM Maximum Input frequency 150 MHz

 

snap to section secure digital io

SECURE DIGITAL I/O

  • Advanced Certus IO libraries include a 1.8V / 3.3V Secure Digital (SD) compliant IO cell.
    • Compatible with DS, HS, SDR25, SDR50, SDR104 and DDR50 protocols.
  • Cell features include:
    • Dynamically Switchable 1.8V & 3.3V VDDIO support
    • Output enable
    • Hysteresis receiver
    • Full interoperability with Certus GPIO library
    • ESD protection of 2KV HBM, 500V CDM1
      1CDM rating is a function of package size. Rating shown is for nominal packages.

Pin

Description

VDDIO 1.8V/3.3V selectable
VDD Core Supply
VSS 0V GND
DIN Core data to PAD
OE Output Enable (HiZ when disabled)
DOUT PAD data to core
PAD Bond pad to outside world

 

Key Secure Digital Specifications

Description

Min

Nom

Max

Units

VDDIO IO supply voltage (3.3V mode) 3.0 3.3 3.63 V
IO supply voltage (1.8V mode) 1.62 1.8 1.98 V
Tj Operating temperature range (junction) -40 25 125 °C
VIH Input logic high (3.3V mode) 1.9 - - V
Input logic high (1.8V mode) 1.1 - - V
VIL Input logic low (3.3V mode) - - 0.9
Input logic low (1.8V mode) - - 0.6 V
VOH Output logic high @-100mA (3.3V mode) 2.25 - - V
Output logic high @-mA (1.8V mode) 1.8 - - V
VOL Output logic low @100mA (3.3 mode) 0 - 0.45 V
Output logic low @2mA (1.8V mode) 0 - 0.45 V
F Clock frequency (3.3V modes) - 50 MHz
Clock frequency (1.8V modes up to SDR50) - 100 MHz

 

snap to section rgmii tsmc offer

Secure Digital TSMC Technology Offerings

Feature

180nm

130nm

65nm

28nm

22nm

16/12nm

VDDIO - - - 1.8V, 3.3V 1.8V, 3.3V 1.8V, 3.3V
VDD - - - 0.9V 0.9V 0.8V
Frequency
(3.3V modes)
- - - 50MHz 50MHz 50MHz
Frequency
(1.8V modes)
- - - 100MHz1 100MHz1 208MHz2
Schmitt - - - Yes Yes Yes
Package - - - Wirebond Wirebond Flip-Chip
Cell pitch - - - 55/25/20um 55um 25um

1The 28nm & 22nm SD IO is capable of supporting up to SDR50
2The 16/12nm SD IO can additionally support SDR104

snap to section hv and custom cells

HV & Custom Cells

  • Certus offers high-voltage ESD solutions achieving 10V, 15V and even 20V in baseline CMOS technologies, enabling co-integration with conventional CMOS designs and keeping processing costs to a minimum.
  • Specialty cell offerings include low-capacitance RF, small-footprint ESD, and even through-silicon via. Certus can create custom cells in any node to fit your requirements.

Select Your Technology Node

GlobalFoundries

Samsung

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