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# Certus Semiconductor

Custom RF/Analog, IO, and ESD Solutions

## Sitemaps

- [XML Sitemap](https://certus-semi.com/sitemap.xml): Contains all public & indexable URLs for this website.

## Posts

- [CDM Dependence on Device Capacitance](https://certus-semi.com/cdm-dependence-on-device-capacitance/) - Introduction In a previous blog “Field Induced CDM Explained” I discussed what happens during the CDM test. This included the sequence of events as voltage is applied to the field plate, how the potential on the device under test (DUT) tracks the field plate, and how the DUT actually becomes charged when the pogo pin
- [Low-Leakage Digital Design on SkyWater 90nm](https://certus-semi.com/low-leakage-digital-design-on-skywater-90nm/) - A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library As semiconductor designs continue to diversify, many successful products are not chasing the most advanced process nodes. Instead, they prioritize power efficiency, reliability, and long-term availability. Mature nodes such as SkyWater 90nm (S90 / C9) remain an excellent choice for industrial, aerospace,
- [Modern Trends in I/O and ESD Design](https://certus-semi.com/modern-trends-in-i-o-and-esd-design/) - It was very clear at the recent 2025 TSMC OIP Ecosystem Forum that the semiconductor I/O landscape has undergone a profound transformation over the past 25 years, evolving from simple general-purpose input/output (GPIO) cells in 180nm nodes to highly complex, multi-protocol, feature-rich libraries in advanced 16nm and 22nm processes. As Stephen Fairbanks, CEO of Certus Semiconductor, outlines in
- [Field Induced CDM Explained](https://certus-semi.com/field-induced-cdm-explained/) - Preface This blog post is an update of an article originally published in 2008 in the now defunct Conformity magazine. The original article is available elsewhere on the Minotaur Labs web site, but changes in the test standards for electrostatic discharge (ESD) have changed sufficiently to warrant a “freshening” of the article. Since that time
- [One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies](https://certus-semi.com/one-platform-five-libraries-certus-semiconductors-i-o-ip-portfolio-for-every-application-on-tsmc-22nm-ull-ulp-technologies-2/) - May 28, 2025 Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our
- [Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions](https://certus-semi.com/certus-semiconductor-joins-tsmc-ip-alliance-program-to-enhance-custom-i-o-and-esd-solutions/) - April 23, 2025 Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions [Santa Clara, CA / April 23, 2025] – Certus Semiconductor, a leading provider of custom I/O and ESD Solutions to the semiconductor industry, is announcing an official partnership to join the TSMC Intellectual Property (IP) Alliance program, a
- [Unlocking High-Speed Connectivity with Certus Semiconductor’s LVDS Transceiver on GlobalFoundries 12LP/LP+](https://certus-semi.com/unlocking-high-speed-connectivity-with-certus-semiconductors-lvds-transceiver-on-globalfoundries-12lp-lp/) - In today’s data-driven world, high-speed, low-power communication is essential. Certus Semiconductor’s LVDS Transceiver delivers exactly that—optimized for GlobalFoundries’ 12nm CMOS process, it provides reliable, high-performance Low-Voltage Differential Signaling (LVDS) for next-generation designs. Built for Performance: This 0.8V LVDS transceiver is built on GlobalFoundries' advanced 12nm process, leveraging: -0.8V core devices & 1.8V I/O devices for
- [Join the Discussion: Foundry ESD Checks & Standardized ESD Compact Models at US-IEW 2025](https://certus-semi.com/join-the-discussion-foundry-esd-checks-standardized-esd-compact-models-at-us-iew-2025/) - The ever-evolving landscape of semiconductor design demands robust ESD protection strategies that balance performance, reliability, and compliance. At the 2025 International Electrostatic Discharge Workshop (US-IEW), industry leaders will come together to tackle two of the most pressing topics in ESD: Foundry ESD Checks and IC Requirements and Standardized ESD Compact Models. We’re excited to announce
- [Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+](https://certus-semi.com/certus-releases-radiation-hardened-i-o-library-in-globalfoundries-12nm-lp-lp/) - Certus Semiconductor is pleased to announce that it has begun 2025 with the delivery of a radiation-hardened by design I/O library in GlobalFoundries 12nm LP/LP+ technology to a tier one customer. This design incorporates silicon-proven ESD that had been delivered previously to another tier one customer. The library includes a 1.8V and 3.3V GPIO with
- [Why CDM?](https://certus-semi.com/why-cdm/) - The qualification requirements for integrated circuits for both JEDEC [1] and the Automotive Electronics Council (AEC) [2], require ESD testing for both Human Body Model (HBM) and Charged Device Model (CDM). Despite this requirement, examination of integrated circuit datasheets often does not include ESD data, and when they do it is overwhelmingly HBM data, with
- [HBM Pin Combinations](https://certus-semi.com/hbm-pin-combinations/) - Introduction In a previous blog, HBM Basic Waveform, we discussed the circuit diagram and basic waveform for the Human Body Model (HBM) ESD stress test. That blog did not, however, address how the HBM waveform is applied to an integrated circuit. The device under test (DUT) was simply represented as a 2-pin device. One possibility
- [Human Body Model (HBM) Waveform](https://certus-semi.com/human-body-model-hbm-waveform/) - Our first post of this series will discuss the Human Body Model (HBM) waveform. The HBM test is intended to simulate an electrostatically charged person discharging through an integrated circuit. If you look at the latest version of the joint JEDEC/ESDA HBM standard, ANSI/ESDA/JEDEC JS-001-2017, you will see a circuit diagram similar to the one
- [Certus Semiconductor releases I/O library in TowerJazz's 65nm process](https://certus-semi.com/certus-semiconductor-releases-i-o-library-in-towerjazzs-65nm-process/) - Certus is excited to announce that its 1.2V/3.3V wire-bond I/O library in TowerJazz’s 65nm process is silicon-verified, and exceeding expectations! This is a Foundation I/O library featuring 8kV HBM and >500V CDM ESD protection, standard, in all I/O’s and Powers, ensuring robust reliability in challenging environments. The library’s compact footprint (70x100um), crafted explicitly for space-efficient
- [The 2024 Design Automation Conference and Certus Semiconductor](https://certus-semi.com/the-2024-design-automation-conference-and-certus-semiconductor/) - DAC is right around the corner and this could possibly be the last one in San Francisco for a while so do not miss it. The weather will be absolutely great and there are many things to do outside of the conference including sailing on the bay. The Design Automation Conference (DAC) is a premier event that
- [HBM Pin Combinations - Table 2A](https://certus-semi.com/hbm-pin-combinations-table-2a/) - Introduction In previous blog posts, we have discussed the Human Body Model (HBM) waveform and traditional HBM pin combinations. In this post I will discuss the updated pin combinations available in the HBM standard JS-001 2017 and the motivations for those pin combinations. Unless you are familiar with the traditional HBM pin combinations I would
- [HBM: 10kOhm Option](https://certus-semi.com/hbm-10kohm-option/) - In an earlier blog the basic HBM waveform was discussed and Figure 1 was used to introduce how the waveform was formed. The JS-001 HBM standard shows a somewhat more detailed figure, which is reproduced in Figure 2. The two figures are essentially identical except for the Charge Removal Circuit in Figure 2. In this
- [2024 Outlook with Stephen Fairbanks of Certus Semiconductor](https://certus-semi.com/2024-outlook-with-stephen-fairbanks-of-certus-semiconductor/) - Certus Semiconductor is a unique company. Their customer centric business model ensures customer success at many levels. Certus is staffed by a team of IO and ESD experts that go above and beyond what you can get from free libraries, protecting your designs and your customers products from the risks of electrostatic discharge. Tell us
- [Machine Model (MM) - Don't Do It](https://certus-semi.com/machine-model-mm-dont-do-it/) - Traditionally there have been three test methods for evaluating the robustness of integrated circuits to electrostatic discharge (ESD) damage during manufacturing, Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Recently MM has fallen out of favor and is no longer a requirement nor accepted test for qualification based on either the
- [Multi-Protocol and Electrical IO Flexibility Catered for Automotive and Mobile Applications](https://certus-semi.com/multi-protocol-and-electrical-io-flexibility-catered-for-automotive-and-mobile-applications/) - Abstract Modern technology trends are blurring the lines of applications across market domains, forcing products to address multiple industry features simultaneously. With the increase in automotive infotainment systems, autonomous driving, and vision/lidar systems, we now see a convergence of requirements across consumer electronics, mobile communications, and advanced computing platforms. This convergence brings the need for
- [High Voltage (>10V) RF and Analog Interfaces for Standard Low Voltage CMOS TSMC Processes](https://certus-semi.com/high-voltage-10v-rf-and-analog-interfaces-for-standard-low-voltage-cmos-tsmc-processes/) - Authors: Pradeep Thiagarajan and Stephen Fairbanks We live in a digital age, but the world around us is very much analog. Sensors and signal converters exist at the boundaries of digital and analog components, and these boundaries create voltage barriers many times. The need for high performance computing has further forced the foundry technology
- [Certus Semiconductor Partners with Pragma Design for Embedded ESD Detection Technology](https://certus-semi.com/certus-semiconductor-partners-with-pragma-design-for-embedded-esd-detection-technology/) - Certus Semiconductor is delighted to announce a strategic collaboration with Pragma Design, a distinguished name in innovative electronic design solutions. This partnership marks a significant leap forward in advancing Embedded Electrostatic Discharge (ESD) Detection Technology. Embedded ESD Detection Technology Overview: Embedded ESD Detection Technology holds paramount importance in fortifying electronic devices against Electrostatic Discharge,
- [The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries](https://certus-semi.com/the-opportunity-costs-of-using-foundry-i-o-vs-high-performance-custom-i-o-libraries/) - The original vision for Certus Semiconductor in 2008 was to leverage production I/O Libraries from more significant partners, starting with Freescale, and take it to smaller external customers for licensing. This IP was proven and validated, with an excellent silicon track record and big company support; in our minds, we thought, “What small company wouldn’t
- [Unique IO & ESD Solutions @ DAC 2023!](https://certus-semi.com/unique-io-esd-solutions-dac-2023/) - The semiconductor industry drives innovation and constantly seeks methods to lower costs and improve performance. The advantages of custom I/O libraries versus free libraries can be seen as cost-savings or, more importantly, new markets, new customers, and new business opportunities. At DAC 2023, Certus Semiconductor will share the advantages of high-performance I/O libraries and having the opportunity to
- [CEO Interview: Stephen Fairbanks of Certus Semiconductor](https://certus-semi.com/ceo-interview-stephen-fairbanks-of-certus-semiconductor/) - CEO Background Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight mass spectrometer. Soon after, he joined Intel,
- [October 2013 - October 2020 News](https://certus-semi.com/october-2013-october-2020-news/) - October 2020 Certus Semiconductor is now listed on ChipEstimate.com, with updated IP listings including our new 11nm Samsung I/O Library! September 2020 CTO Stephen Fairbanks comes out of the design cave long enough to clean up and take a new profile picture! April 2019 Certus Semiconductor Joins Silicon Catalyst In-Kind Partner Program Silicon Valley, CA., Silicon Catalyst,
- [TSMC 180nm, 130nm and 110nm nodes Release](https://certus-semi.com/tsmc-180nm-130nm-and-110nm-nodes-release/) - The Certus design team is constantly expanding our collection of high-performance Digital and Analog IO. In May their customers released three new chips in TSMC 180nm, 130nm and 110nm nodes. These IC’s included specialized Certus IO technologies. One such example was a 1.2V to 3.3V capable multi-function GPIO that’s is able to fully comply with
- [TSMC 55nm is a GPIO Library with specialized interface capabilities.](https://certus-semi.com/tsmc-55nm-is-a-gpio-library-with-specialized-interface-capabilities/) - Our latest release on TSMC 55nm is a GPIO Library with specialized interface capabilities such as MIPI Soundwire and I2C. These deluxe cells include trimmable timing, clock phase selector, multiple input/output/ hi-Z modes, power down mode, analog test points, and ultra-low leakage regardless of power sequencing. A GPIO with a high-Voltage feature for VPP programming
- [Certus Semiconductor Partners With ASK Radio Systems](https://certus-semi.com/certus-semiconductor-partners-with-ask-radio-systems/) - Certus Semiconductor is pleased to announce their strategic partnership with ASK Radio Systems. Along with their decades of expertise in RF and Analog circuit design, ASK Radio Systems brings a catalog of PLLs, LNAs, Power Amplifiers, and full transceivers for LTE, WiFi, GPS, and more. Certus CTO Stephen Fairbanks says, “Their Analog experience is a perfect
- [Design Automation Conference December 2021](https://certus-semi.com/design-automation-conference-december-2021/) - We loved seeing so many of you this week in San Francisco. Design Automation Conference was well attended despite the pandemic, and everyone seemed excited to be back in-person. It was our first year to be an exhibitor, and we’re grateful to all of our supporters that stopped in to see our booth. For those
- [Certus Semiconductor exhibited for the second time at DAC 59 in San Francisco](https://certus-semi.com/certus-semiconductor-exhibited-for-the-second-time-at-dac-59-in-san-francisco/) - Certus Semiconductor exhibited for the second time at DAC 59 in San Francisco. It was a very exciting conference, and it was so good to see so many innovators and groundbreakers in the same room.
- [Kaviaz Technology becomes official distributor for the Taiwan market](https://certus-semi.com/kaviaz-technology-becomes-official-distributor-for-the-taiwan-market/) - Certus Semiconductor is proud to make Kaviaz Technology our official distributor for the Taiwan market. Kaviaz works with major international vendors to provide customers the best EDA tools/silicon IP solutions and services.
- [Certus Semiconductor releases ESD library in GlobalFoundries 12nm Finfet process](https://certus-semi.com/certus-semiconductor-releases-esd-library-in-globalfoundries-12nm-finfet-process/) - Certus is pleased to announce the release of our ESD library in GlobalFoundries 12nm Finfet process. It offers a wide range of generic voltage solutions: 0.8V, 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V for power domains and I/Os. The library provides ESD solutions from 500V to >8kV HBM; 3A to 12A CDM options targeting 250V to
- [Certus Semiconductor introduces new Chief Operating Officer, Andres Rodriguez](https://certus-semi.com/certus-semiconductor-introduces-new-chief-operating-officer-andres-rodriguez/) - Certus Semiconductor is pleased to introduce our new Chief Operating Officer, Andres Rodriguez. Andres is excited to enter the semiconductor industry. Prior to joining Certus, he served in the United States Marine Corps, with ten years of active service as an infantry officer. He was also the Battalion Executive Officer for 2nd Battalion, 1st Marines
- [Certus Semiconductor becomes member of Global Semiconductor Alliance (GSA)](https://certus-semi.com/certus-semiconductor-becomes-member-of-global-semiconductor-alliance-gsa/) - Certus Semiconductor, an innovative leader in custom I/O and ESD design that provides the most efficient and competitive solutions for a customer’s specific market, is pleased to announce that they have become a member of Global Semiconductor Alliance (GSA), the voice of the global semiconductor industry. “GSA is a vital element of the semiconductor industry, where leaders
- [August 2014 News](https://certus-semi.com/august-2014-news/) - Certus announces a silicon validated series of Extreme High Voltage design solutions for building 10-30V applications in a variety of standard foundry low voltage CMOS processes. TSMC Processes: Exotic High Voltage ESD Protection
- [June 2014 DAC Conference](https://certus-semi.com/june-2014-dac-conference/) - Catch us at DAC 2014 (Design Automation Conference) and more importantly, do not miss our Stars of IP Party
- [June 2014 News](https://certus-semi.com/june-2014-news/) - Certus release a silicon Validated 28nm Pad and IO Library in 28nm TSMC. This unique Library includes dynamic mulit-voltage VDDIO from 1.8V to 3.3V, robust ESD and even 2kV IEC, and an extremely flexible feature set. TSMC 28nm Custom IO and ESD Library: Multi-Voltage
- [April 2013 News](https://certus-semi.com/april-2013-news/) - Stephen Fairbanks, Managing Director at Certus-Semiconductor is interviewed by Warren Savage of Take Five, a series of interviews with leaders in the semiconductor industry. Warren Savage and Stephen Fairbanks, "Take Five with Warren" Also Stephen presented at the GSA (Global Semiconductor Alliance) 3D-IC working group. 3D IC Integration and ESD
- [October 2013 News](https://certus-semi.com/october-2013-news/) - Catch us at the Smeico IMPACT Conference 2013 View the Certus Presentation at the conference here: Do you know what ESD really is?
- [January 2013 News](https://certus-semi.com/january-2013-news/) - Certus release a silicon Validated 65nm Pad and IO Library in 65nm Global Foundries. Includes LVDS RX/TX PHY macros. GF 65nm GPIO and LVDS Library (with RF and Analog)
- [March 2013 News](https://certus-semi.com/march-2013-news/) - Stephen Fairbanks, Managing Dirertor at Certus Semiconductor, will offer a webinar for the Constellations Educational Webinar Series. EOS vs. ESD: Understanding the Confusion
- [September 2012 News](https://certus-semi.com/september-2012-news/) - Catch us at the IP Extreme Constellations Conference Oct 4 http://www.ip-extreme.com/news/constellations2012.shtml Watch Stephen Fairbanks, Managing Director at Certus Semiconductor offer a presentation at the conference: The Black Magic of ESD and I/O Design
- [April 2012 News](https://certus-semi.com/april-2012-news/) - Certus Semiconductor is proud to announce its membership with IPextreme's Constellations Program. IPextreme Announces new IP database for Constellations Program
- [September 2011 News](https://certus-semi.com/hello-world/) - Certus Semiconductor makes available TSMC 28nm ESD Libraries based on Freescale IP.
- [February 2011](https://certus-semi.com/hello-world-3/) - Certus Semiconductor makes available >2kV HBM/500V CDM ESD protection library in TSMC 40nm Technology for 28Gbit CMOS interfaces.
- [August 2009 News](https://certus-semi.com/hello-world-2/) - Certus Semiconductor announces a Technologies transfer and License agreement with Freescale Semiconductor. Freescale grants Certus the right to utilize and market ESD and IO products and services utilizing Freescale’s industry-leading ESD technology and IP. Certus Freescale Press Release, August 2009

## Pages

- [Home](https://certus-semi.com/) - We have assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products.
- [Contact](https://certus-semi.com/contact/) - YOUR CHOICE PROVIDER FOR IO & ESD LIBRARY SOLUTIONS Contact Certus Semiconductor 10628 E. Diffraction Ave Mesa, AZ 85212 Email: info@certus-semi.com Taiwanese Office Kaviaz Technology Co., Ltd 8F-1, No.285, Sec. 2, Guangfu Rd., Hsinchu 30071, Taiwan Phone：+886-3-516-3168 Email: info@kaviaztech.com Israel and Eastern European Office Kal Silicon Technologies Contact: Adi Katav POB 712. Kiryat-Ono, 5510602 ISRAEL
- [TSMC IP](https://certus-semi.com/tsmc-ip-offerings/) - TSMC IP Certus Semiconductor is a member of TSMC's IP Alliance Program 180nm RS18: 1.8V GPIO with 1.8V/3.3V analog I/O MS18: 1.2V-1.8V GPIO with 1.8V/5V analog/RF, 20-36V HV analog & OTP HS18: 1.8V to 5V GPIO & analog I/O Library 130nm VR13: Radiation-Hardened wirebond I/O Library (GPIO, LVDS, I2C ODIO, analog,
- [Samsung, Dongbu HiTek, UMC, Tower, Skywater IP](https://certus-semi.com/samsung-dongbu-hitek-tpsco-skywater/) - Samsung, Dongbu HiTek, UMC, Tower, Skywater IP Samsung Samsung 11nm: 1.8V/3.3V Switchable GPIO with 5V I2C ODIO & Analog Cells Dongbu HiTek DN130: 5V fail-safe GPIO, GPI, & I2C ODIO library DN110: Multi-Voltage 1.2-3.3V fail-safe GPIO/ODIO with analog mux Tower JA65: High-Speed 3.3V Wire-bond I/O Library with 1.2Gbps LVDS TX, 8kV HBM ESD and I2C
- [GlobalFoundries IP](https://certus-semi.com/globalfoundries-ip-offerings/) - GlobalFoundries IP Certus Semiconductor is a member of GlobalFoundries' GlobalSolutions Ecosystem Program 180nm TA18: 1.5V - 3.3V GPIO Library with tri-state driver & 7V OTP\ Specialized 5V ESD Clamp 65nm DSO65: 2.5V GPIO Library with Integrated 2Gbps LVDS TX/RX & analog/RF 55nm VZ55: 1.8V/3.3V GPIO with I2C ODIO & analog I/O VY55: 3.3V GPIO
- [Silicon IP](https://certus-semi.com/foundries/) - OUR DOCUMENTATION We Offer A Wide Variety Of Information Certus has silicon-proven libraries in the following foundry processes. These can be licensed off-the-shelf or can be customized for your application, and are available as full libraries or on a cell-by-cell basis. In addition to these processes, we have consulted on designs in many others and
- [Specialty ESD](https://certus-semi.com/specialty-esd/) - Specialty ESD Certus provides ESD protection to meet your every need. ESD circuits that offer ultra-low capacitance or extreme protection, and everything in between. We work with your team to pinpoint the exact amount of protection needed, limiting waste. Specialty ESD Your applications strive to address an ever-changing and complex world. We develop specialty ESD
- [About Us](https://certus-semi.com/about-us/) - Learn More About Certus → About Us Our Team Our Partners Testimonials About Us / Our Team / Our Partners / Testimonials ABOUT CERTUS SEMICONDUCTOR Certus Semiconductor is a Unique IO & ESD Solution Company We have assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability
- [Test page](https://certus-semi.com/test-page/) - TSMC IP Offerings 180nm 1.2V-1.8V GPIO with Ultra-Low Leakage, Low-Cap, 1.8/5V & 20V-36V HV Analog 1.8V GPIO, 1.8V & 3.3V Analog, Custom Low Leakage 3.3V Analog I/O (Contact Us) 6.5V ESD Power Clamp (Contact Us) 130nm 1.2V to 3.3V Rad-Hard Multi-Voltage GPIO and Analog I/O, Includes RF Analog and Integrated 100MBps LVDS TX and RX
- [Design Services](https://certus-semi.com/design-services/) - OUR DESIGN SERVICES Certus Offers The Following Design Services RF/Analog Circuit Characterization and Design PLLs, Amplifiers, Drivers, PHY Blocks Liberty Timing Modeling Large and complete .LIB models for I/O’s and Standard Cell Libraries IBIS Models for I/O’s Custom Standard Cell Libraries In many cases 1-off standard cell designs for integration into Foundry Libraries I/O
- [Digital I/O](https://certus-semi.com/digital-i-o/) - Select A Solution → GPIO ODIO High Speed Differential GPIO / ODIO / High-Speed Differential Digital I/O In Fact, They Can Be Incredibly Powerful. Certus Semiconductor offers numerous libraries of Digital I/Os to meet the needs of your specific project. Our Multitool specialty circuit is capable of meeting many GPIO/ODIO standards and many of our
- [Analog I/O](https://certus-semi.com/analog-i-o/) - Select A Solution → Ultra-Low C Ultra ESD Ultra Volt Ultra-Low C / Ultra ESD / Ultra Volt Analog I/O Get ESD Protection For An Analog Component ESD circuits that offer ultra-low capacitance or extreme protection, and everything in between. We work with your team to pinpoint the exact amount of protection needed, limiting waste.
- [Privacy Policy](https://certus-semi.com/privacy-policy/) - This privacy notice for SRF Technologies, LLC dba Certus Semiconductor ("Company," "we," "us," or"our"), describes how and why we might collect, store, use, and/or share ("process") your information when you use our services ("Services"), such as when you: Visit our website at https://certus-semi.com, or any website of ours that links to this privacy notice Engage
- [Thank You](https://certus-semi.com/thank-you/) - Thank you for your submission. We will be contacting you soon!
- [News & Blog](https://certus-semi.com/news-and-blog/)
- [Digital & Analog IP](https://certus-semi.com/digital-and-analog-ip/) - OUR DIGITAL & ANALOG SERVICES We Offer A Wide Variety Of Services Certus has a Digital and Analog IP across many foundries and nodes. Our off-the-shelf database offers a starting point to affordably create the custom variations you need. We also provide full libraries, complete with Digital I/O, Analog protection, corners, fillers, and auxiliary cells.
- [Testimonials](https://certus-semi.com/testimonials/)
- [Sample Page](https://certus-semi.com/sample-page/) - This is an example page. It's different from a blog post because it will stay in one place and will show up in your site navigation (in most themes). Most people start with an About page that introduces them to potential site visitors. It might say something like this: Hi there! I'm a bike messenger

## Testimonials

- [TDK InvenSense](https://certus-semi.com/testimonial/pruthvi-chaudri/) - Stephen & and the Certus Team [sic] are highly recommended. We engaged with Stephen for (1) IO ESD expertise (2) to serve as an independent reviewer and (3) ~MHz IO designs. Stephen's knowledge ESD designs is commendable. With his help, we were able to interpret TLP data correctly (multi-finger turn-on mechanisms) and discover weaknesses evident
- [Endura Technologies](https://certus-semi.com/testimonial/endura-technologies/) - We reached out to Stephen and the Certus Team for ESD consultation after failing to meet performance on our first product design. They integrated seamlessly with our design team and immediately found our issues and guided our team on the fixes. Our design update now fully meets/exceeds the spec and we are using Certus for
- [Trameto](https://certus-semi.com/testimonial/trameto/) - “Certus Semiconductor helped us created a FIRST SILICON success story.” Huw Davies CEO, Trameto
- [UHNDER](https://certus-semi.com/testimonial/uhnder/) - “The I/O and ESD solutions from Certus provide substantial improvement over the “standard” options.” Paul Basset Principal Engineer, Uhnder, Inc.
- [NXP](https://certus-semi.com/testimonial/nxp/) - “The Certus team was able to use their experience to find a design solution that worked the FIRST TIME and passed our ESD requirements.” Michael Stockinger Technical Director, NXP

## Categories

- [Uncategorized](https://certus-semi.com/category/uncategorized/)