The Certus design team is constantly expanding our collection of high-performance Digital and Analog IO. In May their customers released three new chips in TSMC 180nm, 130nm and 110nm nodes. These IC’s included specialized Certus IO technologies. One such example was a 1.2V to 3.3V capable multi-function GPIO that’s is able to fully comply with SPI, I2C and I3C IO standards, all while exceeding 4kV HBM targets in a footprint smaller than the foundry and competing IO Libraries. Additional silicon proven designs in these releases included a complete Rad-Hard/High Temperature tolerant IO Library with GPIO’s, LVDS PHY’s (TIA-644/Spacewire complaint) and Open-Drain IO’s (Fail-Safe I2C/I3C complainant).
Certus Semiconductor Joins Silicon Catalyst In-Kind Partner Program
Silicon Valley, CA., Silicon Catalyst, the world’s only Incubator focused exclusively on accelerating solutions in silicon, announces the addition of Certus Semiconductor and Silitronics as the newest addition to the continuously expanding ecosystem of In-Kind Partners (IKP). Silicon Catalyst continues to work with key industry players to further develop a complete value chain that economically and effectively supports the semiconductor start-ups accepted into the Incubator. These startups utilize Silicon Catalyst’s world-class network of advisors, design tools, silicon devices, networking, with access to funding and marketing acumen needed to successfully launch their businesses.
Certus announces new 16nm and 12nm Multi-voltage GPIO and ODIO Libraries. Included IP is 5V Open-Drain IO's, 5V LVDS and HDMI ESD Solutions. Low Capacitance RF Solutions with High ESD protection. Contact your Certus Agent for more information.
Certus announces silicon proven Fail-Safe (non-obstruct) versions of our 28nm Multi-Voltage (1.8V to 3.3V) GPIO's in a triple staggered 20um pitch format. Ideal for power sensitive System applications and PAD limited designs.
Certus Announces release of 5V Open-Drain IO's (ODIO) in TSMC 28nm Processes using only 1.8V Transistors. 2kV IEC compliant ODIO available for use in external connectors (i.e USB, HDMI, etc). An addendum to the existing 28nm TSMC 28nm GPIO and HDMI/LVDS/Analog Library.
Certus announces the silicon validated worlds smallest area IO for ESD protection of analog, HDMI and high speed digital circuits in 40nm TSMC. The ESD and power bussess are completely underneath the Bondpad, making the IO cell only 60um x 50um wide/pitch.
Certus announces a silicon validated series of Extreme High Voltage design solutions for building 10-30V applications in a variety of standard foundry low voltage CMOS processes.
Certus release a silicon Validated 28nm Pad and IO Library in 28nm TSMC. This unique Library includes dynamic mulit-voltage VDDIO from 1.8V to 3.3V, robust ESD and even 2kV IEC, and an extremely flexible feature set.
Stephen Fairbanks, Managing Director at Certus-Semiconductor is interviewed by Warren Savage of Take Five, a series of interviews with leaders in the semiconductor industry.
Also Stephen presented at the GSA (Global Semiconductor Alliance) 3D-IC working group.
Catch us at the IP Extreme Constellations Conference Oct 4
Watch Stephen Fairbanks, Managing Director at Certus Semiconductor offer a presentation at the conference:
Certus Semiconductor makes available TSMC 28nm ESD Libraries based on Freescale IP.
Certus Semiconductor makes available >2kV HBM/500V CDM ESD protection library in TSMC 40nm Technology for 28Gbit CMOS interfaces.
Certus Semiconductor announces a Technologies transfer and License agreement with Freescale Semiconductor. Freescale grants Certus the right to utilize and market ESD and IO products and services utilizing Freescale’s industry-leading ESD technology and IP.