July 2021

Our latest release on TSMC 55nm is a GPIO Library with specialized interface capabilities such as MIPI Soundwire and I2C. These deluxe cells include trimmable timing, clock phase selector, multiple input/output/ hi-Z modes, power down mode, analog test points, and ultra-low leakage regardless of power sequencing.  A GPIO with a high-Voltage feature for VPP programming up to 6.5V is also available. Powers include a Core supply down to 0.9V and IO supply up to 1.8V. It is silicon-proven and passes 4kV HBM.

May 2021

The Certus design team is constantly expanding our collection of high-performance Digital and Analog IO. In May their customers released three new chips in TSMC 180nm, 130nm and 110nm nodes.  These IC’s included specialized Certus IO technologies.  One such example was a 1.2V to 3.3V  capable multi-function GPIO that’s is able to fully comply with SPI, I2C and I3C IO standards, all while exceeding 4kV HBM targets in a footprint smaller than the foundry and competing IO Libraries.   Additional silicon proven designs in these releases included a complete Rad-Hard/High Temperature tolerant IO Library with GPIO’s, LVDS PHY’s (TIA-644/Spacewire complaint) and Open-Drain IO’s (Fail-Safe I2C/I3C complainant).

October 2020

Certus Semiconductor is now listed on ChipEstimate.com, with updated IP listings including our new 11nm Samsung I/O Library!

September 2020

CTO Stephen Fairbanks comes out of the design cave long enough to clean up and take a new profile picture!

April 2019

Certus Semiconductor Joins Silicon Catalyst In-Kind Partner Program

Silicon Valley, CA., Silicon Catalyst, the world’s only Incubator focused exclusively on accelerating solutions in silicon, announces the addition of Certus Semiconductor and Silitronics as the newest addition to the continuously expanding ecosystem of In-Kind Partners (IKP). Silicon Catalyst continues to work with key industry players to further develop a complete value chain that economically and effectively supports the semiconductor start-ups accepted into the Incubator. These startups utilize Silicon Catalyst’s world-class network of advisors, design tools, silicon devices, networking, with access to funding and marketing acumen needed to successfully launch their businesses.

TO LEARN MORE: https://siliconcatalyst.com/certus-semiconductor-and-silitronics

July 2018

Robert Ashton over at Minotaur Labs has started a very interesting ESD Testing Blog, we strongly recommend you check it out!

January 2018

Certus announces new 16nm and 12nm Multi-voltage GPIO and ODIO Libraries.  Included IP is 5V Open-Drain IO's, 5V LVDS and HDMI ESD Solutions.  Low Capacitance RF Solutions with High ESD protection.  Contact your Certus Agent for more information.

August 2017

Certus announces silicon proven Fail-Safe (non-obstruct) versions of our 28nm Multi-Voltage (1.8V to 3.3V) GPIO's in a triple staggered 20um pitch format.  Ideal for power sensitive System applications and PAD limited designs.

TSMC 28nm IO Libraries

January 2016

Certus announces 2 new classes of High Voltage, low capcaitance and low leakage, ESD protection structures, in TSMC 180nm Gen2 process.

TSMC 180nm BCD Low Cap High Voltage ESD Protection

July 2015

Certus Announces release of 5V Open-Drain IO's (ODIO) in TSMC 28nm Processes using only 1.8V Transistors.  2kV IEC compliant ODIO available for use in external connectors (i.e USB, HDMI, etc). An addendum to the existing 28nm TSMC 28nm GPIO and HDMI/LVDS/Analog Library.

TSMC 28nm Custom IO and ESD Library: Multi-Voltage 

October 2013

January 2015

Certus announces the silicon validated worlds smallest area IO for ESD protection of analog, HDMI and high speed digital circuits in 40nm TSMC. The ESD and power bussess are completely underneath the Bondpad, making the IO cell only 60um x 50um wide/pitch.

TSMC 40nm: HDMI, LVDS, RF and Analog Pads, worlds smallest footprint cell

October 2014

Catch us at the 2014 Silicon Valley IP Users Conference

If you missed it, make sure to catch the video of  Stephen Fairbanks, Managing Director at Certus Semiconductor, present: How Custom IO can Benefit You

August 2014

Certus announces a silicon validated series of Extreme High Voltage design solutions for building 10-30V applications in a variety of standard foundry low voltage CMOS processes.

TSMC Processes: Exotic High Voltage ESD Protection

June 2014

Catch us at DAC 2014 (Design Automation Conference)

and more importantly, do not miss our Stars of IP Party

June 2014

Certus release a silicon Validated 28nm Pad and IO Library in 28nm TSMC.  This unique Library includes dynamic mulit-voltage VDDIO from 1.8V to 3.3V, robust ESD and even 2kV IEC, and an extremely flexible feature set.

TSMC 28nm Custom IO and ESD Library: Multi-Voltage 

April 2013

Stephen Fairbanks, Managing Director at Certus-Semiconductor is interviewed by Warren Savage of Take Five, a series of interviews with leaders in the semiconductor industry.

Warren Savage and Stephen Fairbanks, "Take Five with Warren"

Also Stephen presented at the GSA (Global Semiconductor Alliance) 3D-IC working group.

3D IC Integration and ESD

October 2013

Catch us at the Smeico IMPACT Conference 2013

View the Certus Presentation at the conference here:

Do you know what ESD really is?

January 2013

Certus release a silicon Validated 65nm Pad and IO Library in 65nm Global Foundries.  Includes LVDS RX/TX PHY macros.

GF 65nm GPIO and LVDS Library (with RF and Analog)

March 2013

Stephen Fairbanks, Managing Dirertor at Certus Semiconductor, will offer a webinar for the Constellations Educational Webinar Series.

EOS vs. ESD: Understanding the Confusion

September 2012

Catch us at the IP Extreme Constellations Conference Oct 4


Watch Stephen Fairbanks, Managing Director at Certus Semiconductor offer a presentation at the conference:

The Black Magic of ESD and I/O Design

April 2012

Certus Semiconductor is proud to announce its membership with IPextreme's Constellations  Program.

IPextreme Announces new IP database for Constellations Program

September 2011

Certus Semiconductor makes available TSMC 28nm ESD Libraries based on Freescale IP.

February 2011

Certus Semiconductor makes available >2kV HBM/500V CDM  ESD protection library in TSMC 40nm Technology for 28Gbit CMOS interfaces.

August 2009

Certus Semiconductor announces a Technologies transfer and License agreement with Freescale Semiconductor.  Freescale grants Certus the right to utilize and market ESD and IO products and services utilizing Freescale’s industry-leading ESD technology and IP.

Certus Freescale Press Release, August 2009