October 2013 – October 2020 News

October 2020

Certus Semiconductor is now listed on ChipEstimate.com, with updated IP listings including our new 11nm Samsung I/O Library!

September 2020

CTO Stephen Fairbanks comes out of the design cave long enough to clean up and take a new profile picture!

April 2019

Certus Semiconductor Joins Silicon Catalyst In-Kind Partner Program

Silicon Valley, CA., Silicon Catalyst, the world’s only Incubator focused exclusively on accelerating solutions in silicon, announces the addition of Certus Semiconductor and Silitronics as the newest addition to the continuously expanding ecosystem of In-Kind Partners (IKP). Silicon Catalyst continues to work with key industry players to further develop a complete value chain that economically and effectively supports the semiconductor start-ups accepted into the Incubator. These startups utilize Silicon Catalyst’s world-class network of advisors, design tools, silicon devices, networking, with access to funding and marketing acumen needed to successfully launch their businesses.

TO LEARN MORE: https://siliconcatalyst.com/certus-semiconductor-and-silitronics

July 2018

Robert Ashton over at Minotaur Labs has started a very interesting ESD Testing Blog, we strongly recommend you check it out!

January 2018

Certus announces new 16nm and 12nm Multi-voltage GPIO and ODIO Libraries.  Included IP is 5V Open-Drain IO's, 5V LVDS and HDMI ESD Solutions.  Low Capacitance RF Solutions with High ESD protection.  Contact your Certus Agent for more information.

August 2017

Certus announces silicon proven Fail-Safe (non-obstruct) versions of our 28nm Multi-Voltage (1.8V to 3.3V) GPIO's in a triple staggered 20um pitch format.  Ideal for power sensitive System applications and PAD limited designs.

TSMC 28nm IO Libraries

January 2016

Certus announces 2 new classes of High Voltage, low capcaitance and low leakage, ESD protection structures, in TSMC 180nm Gen2 process.

TSMC 180nm BCD Low Cap High Voltage ESD Protection

July 2015

Certus Announces release of 5V Open-Drain IO's (ODIO) in TSMC 28nm Processes using only 1.8V Transistors.  2kV IEC compliant ODIO available for use in external connectors (i.e USB, HDMI, etc). An addendum to the existing 28nm TSMC 28nm GPIO and HDMI/LVDS/Analog Library.

TSMC 28nm Custom IO and ESD Library: Multi-Voltage 

October 2013

January 2015

Certus announces the silicon validated worlds smallest area IO for ESD protection of analog, HDMI and high speed digital circuits in 40nm TSMC. The ESD and power bussess are completely underneath the Bondpad, making the IO cell only 60um x 50um wide/pitch.

TSMC 40nm: HDMI, LVDS, RF and Analog Pads, worlds smallest footprint cell

October 2014

Catch us at the 2014 Silicon Valley IP Users Conference

If you missed it, make sure to catch the video of  Stephen Fairbanks, Managing Director at Certus Semiconductor, present: How Custom IO can Benefit You