Our TSMC 130nm IO Library offering includes:
- Built-in 140um inline pitch wirebond pads.
- 3.3V GPIO, I2C open drain cell, LVDS TX & RX cells, analog cell, OTP programming cell & associated ESD.
- Filler, corner, and bus termination cells.
GPIO Features |
| 3.3V VDDIO/1.5V VDD; 50MHz Operation at 15pF |
| Extended operational range of -55°C to 200°C |
| Built-in power regulation PMOS for VDD supply |
| Output Enable (HiZ when disabled) |
| Input enable (input low when disabled) |
| Sleep mode state retention (not shown) |
| Selectable Schmitt trigger receiver |
| 60KΩ selectabe pull-up or pull-down resistor |
| ESD: 2KV HBM, 500V CDM1 |
1CDM rating is a function of package size. Rating shown is for nominal packages.
GPIO Block Diagram
130nm Library Operating Conditions
Parameter |
Value |
| VDDIO
Core VDD |
3.3V ± 10%
1.5V ± 10% |
| Tj
Max_Load |
-55°C to 200°C
15pF |
Power Regulation PMOS
130nm IO library cells feature a built-in power regulation PMOS device and pin (REG) to tie in user-provided regulation circuitry from the core.
130nm Library Cell Size & Metal Stack
Cell Size |
Metal Stack |
Wirebond Pitch |
| 140um x 235um | 8M_6x1z | 140um single row |
Library Cell Summary
Cell Type |
Feature |
| Supply / ESD cells | 3.3V VDDIO; 1.5V VDD; GND
3.3V, 50 MHz (@15pF), sleep retention |
| I2C Open-drain cell
Analog cell OTP Cell Break Cells Filler Cells Corner Cells |
3.3V, 50ns glitch filter, sleep retention
3.3V TX & RX cells, sleep retention 3.3V w/ selectable PD resistor 3.3V programming cell VDDIO, VDD 1um, 5um digital & analog Digital & Analog |
