Our TSMC 16/12nm IO Library offering includes:

  • Flip-chip package support with client-configurable pads.
  • Dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain cell, 1.8V & 3.3V analog cells, HDMI & LVDS protection macros, OTP cell& associated ESD.
  • Domain break cells.
  • Identical feature sets across 16nm and 12nm process technologies.

GPIO Features

Dynamic 1.8V / 3.3V switchable operation
4 selectable drive strengths (DS)
Full-speed output enable/disable (HiZ when disabled)
Independent power sequencing
50Ω (±20%) source termination across PVT
Schmitt trigger receiver
50KΩ selectable pull-up or pull-down resistor
ESD: 2KV HBM, 500V CDM1, 2KV IEC 61000-4-22

1CDM rating is a function of package size. Rating shown is for nominal packages.
2Please contact a Certus representative for IEC 62100-4-2 protection levels achievable with your design.

GPIO Block Diagram

Drive Strength Performance (@10pF)

DS 1.8V 3.3V
00 25MHz 15MHz
01 140MHz 75MHz
10 200MHz 150MHz
11 235MHz 175MHz

16/12nm Library Operating Conditions

Parameter

Value

VDDIO

VREF

Core VDD

1.8V ± 10%, 3.3V ± 10%

1.8V ± 10%

0.8V ± 10%

Tj

Max_Load

-40°C to 125°C

50pF (10pF at speed)

16/12nm Library Cell Size & Metal Stack

Cell Size Metal Stack Package
30um x 50um 1P_8M

1P_10M

Flip-Chip

Library Cell Summary

Cell Type

Feature

Supply/ESD Cells

GPIO cell1

 

RGMII cell

Secure Digital Cell

I2C Open-drain cell2

Analog cells

HDMI macro3

LVDS macro3

OTP cell

1.8V/3.3V VDDIO; 1.8V VREF; 0.8V VDD; GND

25-235MHz @1.8V (selectable)

15-175MHz @3.3V (selectable)

1.8V, 125MHz

3.3V, 50MHz | 1.8V, 208MHz

3.3V-5V, fail-safe

1.8V & 3.3V

3.3V, 5V tolerant, fail-safe

1.8V

5V programming gate cell

 

Break cells

VDDIO, VDD, VSS

1GPIO speeds are load dependent (faster for lighter loads, slower for heavier). Speeds shown are at 10pF
2Open drain cell is I2C, SMBus, DDC, CEC & HPD compliant
3Solution provides optimized low-capacitance ESD protection only