Our TSMC 22nm IO Library offering includes:
- Built-in 55um inline pitch wirebond pads.
- Dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain cell, 1.8V & 3.3V analog cells & associated ESD.
- Filler, break, and transition cells.
GPIO Features |
| Dynamic 1.8V / 3.3V switchable operation |
| 25MHz, 75MHz & 150MHz speed options1 |
| Full-speed output enable/disable (HiZ when disabled) |
| Independent power sequencing |
| Shorted output protection (fail safe) |
| Schmitt trigger receiver |
| 60KΩ selectable pull-up or pull-down resistor |
| ESD: 2KV HBM, 500V CDM2, 2KV IEC 61000-4-23 |
1GPIO speeds are load dependent (faster for lighter loads, slower for heavier). Speeds shown are at 10pF
2CDM rating is a function of package size. Rating shown is for nominal packages.
3Please contact a Certus representative for IEC 62100-4-2 protection levels achievable with your design
22nm Library Operating Conditions
Parameter |
Value |
| VDDIO
VREF (for 3.3V operation) Core VDD |
1.8V ± 10%, 3.3V ± 10%
1.8V ± 10% 0.9V ± 10% |
| Tj
Max_Load |
-40°C to 125°C
50pF (10pF at speed) |
22nm Library Cell Size & Metal Stack
| Cell Size | Metal Stack | WireBond Pitch |
|---|---|---|
| 55um x 81um | 8M_5x2r | 55um single |
Library Cell Summary
Cell Type |
Feature |
|
Supply/ESD Cells GPIO cells1 RGMII Cell I2C Open-drain cell2 |
1.8/3.3V VDDIO; 1.8V VREF; 0.9V VDD; GND
25MHz, 75MHz, 150 MHz options (fail-safe) 1.8V, 125MHz 3.3V, 50MHz | 1.8V, 100MHz 1.8-3.3V, fail-safe |
| Analog cells
Break cells Filler cells Transition |
1.8V & 3.3V
VDDIO, VDD, VSS 1um, 5um Bridge to TSMC IOs |
1GPIO speeds are load dependent (faster for lighter loads, slower for heavier). Speeds shown are at 10pF
2Open drain cell is I2C, SMBus, DDC, CEC & HPD compliant
