Our TSMC 28nm IO Library offering includes:
- Support for HPM and HPC+ process options.
- Wirebond configurations across a variety of metal stacks and pad arrangements from 55um inline to 20um staggered.
- Dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain cell, 1.8V & 3.3V analog cells, HDMI & LVDS protection macros, OTP cell and associated ESD.
GPIO Features |
Dynamic 1.8V / 3.3V switchable operation |
25MHz, 75MHz & 150MHz speed options1 |
Full-speed output enable/disable (HiZ when disabled) |
Independent power sequencing |
Shorted output protection (fail safe) |
Schmitt trigger receiver |
60KΩ selectable pull-up or pull-down resistor |
ESD: 2KV HBM, 500V CDM2, 2KV IEC 61000-4-23 |
1GPIO speeds are load dependent (faster for lighter loads, slower for heavier). Speeds shown are at 10pF.
2CDM rating is a function of package size. Rating shown is for nominal packages.
3Please contact a Certus representative for IEC 62100-4-2 protection levels achievable with your design.

28nm Library Operating Conditions
Parameter |
Value |
VDDIO
VREF (for 3.3V operation) Core VDD |
1.8V ± 10%, 3.3V ± 10%
1.8V ± 10% 0.9V ± 10% |
Tj
Max_Load |
-40°C to 125°C
50pF (10pF at speed) |
snap to section 28nm Library Size
28nm Library Cell Size & Metal Stack
Option | Cell Size | Metal Stack | WireBond Pitch |
---|---|---|---|
1 | 55um x 75um | 6M_4x1z | 55um single |
2 | 25um x 130um | 7M_5x1z | 25um dual |
3 | 25um x 130um | 9M_6x2z | 25um dual |
4 | 18um x 180um | 9M_6x2z | 20um triple |

Option 1
- 6 metals, 55um single-row pad pitch
- Advantages: reduced cost & inline area optimization

Options 2&3
- 7 or 9 metals, 25um dual row pad pitch
- Advantages: 2 cost points, 2x perimeter efficiency

Option 4
- 9 metals, 20um triple row pad pitch
- Advantage: 25% additional perimeter efficiency
Library Cell Summary
Cell Type |
Feature |
Supply/ESD cells GPIO cells1 RGMII cell I2C Open-drain cell2 |
1.8 / 3.3V VDDIO; 1.8V VREF; 0.9V VDD; GND
25MHz, 75MHz, 150 MHz options (fail safe) 1.8V, 125MHz 3.3V, 50MHz | 1.8V, 100MHz 1.8-5V, fail-safe |
Analog cells
HDMI macro3 LVDS macro3 OTP cell Break cells Filler cells Transition |
1.8V & 3.3V
3.3V, 5V tolerant, fail-safe 1.8V 5V programming gate cell VDDIO, VDD, VSS 1um, 5um Bridge to TSMC native IOs |
1GPIO speeds are load dependent (faster for lighter loads, slower for heavier). Speeds shown are at 10pF
2Open drain cell is I2C, SMBus, DDC, CEC & HPD compliant
3Solution provides optimized low-capacitance ESD protection only.
