Our TSMC 65nm IO Library offering includes:
- Built-in 55um inline pitch wirebond pads.
- Dual independent IO supply rails (1.0-3.3V & 3.3V) and controls to place IOs in a low-power HiZ state during power-down.
- Pulse-width modulation (PWM) output cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP programming cell & associated ESD.
- Filler, corner, and digital / analog bus break cells.
GPIO Features |
| 1.0 - 3.3V & 3.3V dual IO supply rails; 1.2V core VDD |
| 50MHz (1.0 - 3.3V supply) | 100 MHz (3.3V supply) @10pF |
| Output enable (HiZ when disabled) |
| Controls for HiZ during power-down (not shown) |
| Schmitt trigger receiver |
| 55KΩ selectabe pull-up or pull-down resistor |
| ESD: 2KV HBM, 500V CDM1 |
1CDM rating is a function of package size. Rating shown is for nominal packages.
GPIO Block Diagram
65nm Library Operating Conditions
Parameter |
Value |
| VDDIO
Core VDD |
1.0 - 3.3V | 3.3V ± 10% dual rail
1.2V ± 10% |
| Tj
Max_Load |
-40°C to 125°C
15pF |
Power Disable Features
- HiZ state enable via external Power-on-control (POC) cell
- HiZ state enable via core-accessible power enable (PWE) pin
65nm Library Cell Size & Metal Stack
Cell Size |
Type |
Metal Stack |
Wirebond Pitch |
| 55um x 100um
55um x 76um |
Digital
Analog |
7M_4x2z | 55um single row |
Library Cell Summary
Cell Type |
Feature |
| Supply/ESD Cells
GPIO1 cell Power-on-Ctrl cell |
1.0-3.3V & 3.3V VDDIO; 1.2V VDD, GND
50 MHz | 100 MHz Sleep mode enable |
| I2C open drain cell
PWM output cell Analog cells OTP cell Break cells Filler cells |
I2C & SVID variants
Output cell w/midrail disable 3.3V & 5V w/substrate isolation option 5V programming gate cell VDDIO, VDD, VSS 1um, 5um fillers; corner cell |
1GPIO can sustain up to 50MHz on the 1-3.3V rail, 100MHz on the 3.3V rail (up to 10pF load)
